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Integrated Circuit Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
FEATURES
* 9 differential 3.3V LVPECL / ECL outputs * 1 differential LVPECL input pair * PLCK, nPLCK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: >2GHz (typical) * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input * Additive phase jitter, RMS: 0.03ps (typical) * Output skew: 35ps (maximum) * Part-to-part skew: 300ps (maximum) * Propagation delay: 675ps (maximum) * LVPECL mode operating voltage supply range: VCC = 3V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3V to -3.8V * -40C to 85C ambient operating temperature * Lead-Free package RoHS compliant
GENERAL DESCRIPTION
The ICS853111-01 is a low skew, high performance 1-to-9 Differential-to-3.3V LVPECL/ECL HiPerClockSTM Fa n o u t B u f fe r a n d a m e m b e r o f t h e HiPerClock S TM family of High Performance Clock Solutions from ICS. The PCLK, nPCLK pair can accept LVPECL, CML and SSTL differential input levels. The ICS853111-01 is characterized to operate from a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS853111-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
ICS
BLOCK DIAGRAM
PCLK nPCLK Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 V BB Q5 nQ5 Q6 nQ6 Q7 nQ7 Q8 nQ8
PIN ASSIGNMENT
VCCO nQ0 nQ1 nQ2 Q0 Q1 Q2
25 VEE nc PCLK VCC nPCLK VBB nc 26 27 28 1 2 3 4 5
nQ8
24
23
22
21
20
19 18 17 16 Q3 nQ3 Q4 VCCO nQ4 Q5 nQ5
ICS853111-01
15 14 13 12
6
Q8
7
nQ7
8
VCCO
9
Q7
10
nQ6
11
Q6
REV. A APRIL 25, 2005
28-Lead PLCC 11.6mm x 11.4mm x 4.1mm package body V Package Top View
853111AV-01
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Integrated Circuit Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4, 27 5, 6 7, 9 8, 15, 22 10, 11 12, 13 14, 16 17, 18 19, 20 21, 23 24, 25 26 28 Name VCC nPCLK VBB nc nQ8, Q8 nQ7, Q7 VCCO nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 VEE PCLK Power Input Output Unused Output Output Power Output Output Output Output Output Output Output Power Input Pulldown Core supply pin. Pullup/ Inver ting differential LVPECL clock input. Bias to VCC/2 w/no input. Pulldown1 Bias voltage. No connect. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pin. Non-inver ting differential LVPECL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN RPULLDOWN
1
Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Input Pulldown Resistor
Test Conditions
Minimum
Typical 50 75 50
Maximum 1
Units pF K K K
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REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (LVECL mode, VCC = 0) to the device. These ratings are stress specifi-0.5V to V + 0.5 V
CC
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (LVECL mode) Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
0.5V to VEE - 0.5V 50mA 100mA 0.5mA -65C to 150C 37.8C/W (0 lfpm)
cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Temperature Range, TA -40C to +85C
TABLE 3A. LVPECL POWER SUPPLY DC CHARACTERISTICS, VCC = 3V TO 3.8V; VEE = 0V
Symbol VCC VCCO IEE Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.0 3.0 Typical 3.3 3. 3 Maximum 3.8 3.8 75 Units V V mA
Table 3B. LVPECL DC Characteristics, VCC = 3.3V; VEE = 0V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK, nPCLK High Current -40C Min
2.175 1.405 2.075 1.43 1.86 150 1.2 800
25C Max
2.38 1.68 2.36 1.765 1.98 1200 3.3 150
85C Max
2.37 1.615 2.36 1.765 1.98
Typ
2.275 1.545
Min
2.225 1.425 2.075 1.43 1.86 150 1.2
Typ
2.295 1.52
Min
2.295 1.44 2.075 1.43 1.86 150 1.2
Typ
2.33 1.535
Max
2.365 1.63 2.36 1.765 1.98
Units
V V V V V V V A A
800
1200 3.3 15 0
800
1200 3. 3 150
Input -150 -150 -150 PCLK, nPCLK Low Current Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
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REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
Test Conditions Minimum -3.0 Typical -3.3 55 Maximum -3.8 Units V mA
TABLE 3C. ECL POWER SUPPLY DC CHARACTERISTICS, VCC = 0V; VEE = -3V TO -3.8V
Symbol VEE IEE Parameter Supply Voltage Power Supply Current
Table 3D. ECL DC Characteristics, VCC = 0V; VEE = -3V to -3.8V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK, nPCLK High Current -40C Min
-1.125 -1.895 -1.225 -1.87 -1.44 150 VEE+1.2V 800
25C Max
-0.92 -1.62 -0.94 -1.535 -1.32 1200 0 150
85C Max
-0.93 -1.685 -0.94 -1.535 -1.32
Typ
-1.025 -1.755
Min
-1.075 -1.875 -1.225 -1.87 -1.44 150 VEE+1.2V
Typ
-1.005 -1.78
Min
-1.005 -1.86 -1.225 -1.87 -1.44 150 VEE+1.2V
Typ
-0.97 -1.765
Max
-0.935 -1.67 -0.94 -1.535 -1.32
Units
V V V V V V V A A
800
1200 0 150
800
1200 0 150
Input -150 -150 -150 PCLK, nPCLK Low Current Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 4. AC CHARACTERISTICS, VCC = 3V TO 3.8V; VEE = 0V OR VCC = 0V; VEE = -3V TO -3.8V
Symbol fMAX tpLH tpHL Parameter Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time 20% to 80% 90 -40C Min Typ >2 350 450 500 600 20 650 750 35 200 0.03 200 315 100 0.03 203 310 95 385 480 Max Min 25C Typ >2 525 620 20 675 760 35 200 0.03 210 300 410 515 Max Min 85C Typ >2 350 650 20 700 785 35 200 Max Units GHz ps ps ps ps ps ps
tsk(o) tsk(pp) tjit
tR/tF
All parameters measured at f 1GHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter at 155.52MHz
= 0.03ps (typical)
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
SCOPE
V CC
nPCLK
LVPECL
V
nQx VEE PCLK
PP
Cross Points
V
CMR
-1.3V 0.3V
V EE
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy
nQx Qx nQy Qy
PART 2 Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
nPCLK PCLK nQ0:nQ8 Q0:Q8
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
tPD
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
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REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows an example of the differential input that can be wired to accept single ended levels. The reference voltage level VBB generated from the device is connected to the
negative input. The C1 capacitor should be located as close as possible to the input pin.
VCC
C1 0.1u CLK_IN
PCLK VBB nPCLK
FIGURE 1. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
FOR
LVPECL OUTPUTS
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
853111AV-01
FIGURE 2B. LVPECL OUTPUT TERMINATION
REV. A APRIL 25, 2005
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Integrated Circuit Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK R2 50
3.3V Zo = 50 Ohm
3.3V
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 3A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
R5 100 - 200 R6 100 - 200 R1 50 R2 50 Zo = 50 Ohm C2 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 PCLK VBB nPCLK PC L K/n PC LK
R4 125
FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V 3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK HiPerClockS PCLK/nPCLK R4 120
3.3V 3.3V Zo = 50 Ohm LVDS R5 100 Zo = 50 Ohm R1 1K R2 1K C1 PCLK C2 VBB nPCLK PC L K /n PC L K
R1 120
R2 120
FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 3F.
HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
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REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
example of the ICS853111-01 LVPECL clock buffer. In this example, the input is driven by an LVPECL driver.
SCHEMATIC EXAMPLE
This application note provides general design guide using ICS853111-01 LVPECL buffer. Figure 4 shows a schematic
Zo = 50 +
Zo = 50
-
VCC
R2 50
R1 50
VCC
C6 (Option) 0.1u
R3 50
Zo = 50 Ohm
Zo = 50 Ohm 3.3V LVPECL R9 50 C8 (Option) 0.1u R10 50 R11 50 R4 1K
1 2 3 4 5 6 7 8
VCCO Q0 nQ0 Q1 nQ1 Q2 nQ2 VCCO
32 31 30 29 28 27 26 25
VCC CLK_SEL PCLK0 nPCLK0 VBB PCLK1 nPCLK1 VEE VCCO nQ9 Q9 nQ8 Q8 nQ7 Q7 VCCO
Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6
24 23 22 21 20 19 18 17
U1 ICS853111
VCC Zo = 50 +
VCC=3.3V
Zo = 50 -
(U1-9)
VCC
(U1-16)
(U1-25)
(U1-32)
(U1-1)
R8 50 R7 50
C1 0.1uF
C2 0.1uF
C3 0.1uF
C4 0.1uF
C5 0.1uF C7 (Option) 0.1u R13 50
FIGURE 4. EXAMPLE ICS853111-01 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC
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9 10 11 12 13 14 15 16
REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853111-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS853111-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 75mA = 285mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 30.94mW = 278.5mW
Total Power_MAX (3.8V, with all outputs switching) = 285mW + 278.5mW = 563.5mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.564W * 31.1C/W = 102C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE JA
FOR
28-PIN PLCC, FORCED CONVECTION
by Velocity (Linear Feet per Minute)
JA
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.8C/W
200
31.1C/W
500
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50 VCCO - 2V
Figure 5. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 0.935V
-V
OH_MAX
) = 0.935V =V - 1.67V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.67V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.935V)/50] * 0.935V = 19.92mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50] * 1.67V = 11.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE FOR 28 LEAD PLCC
by Velocity (Linear Feet per Minute)
JA
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.8C/W
200
31.1C/W
500
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853111-01 is: 265 Pin compatible with MC100LVE111
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REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
PACKAGE OUTLINE - V SUFFIX FOR 28 LEAD PLCC
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 4.19 2.29 1.57 0.33 0.19 12.32 11.43 4.85 12.32 11.43 4.85 MINIMUM 28 4.57 3.05 2.11 0.53 0.32 12.57 11.58 5.56 12.57 11.58 5.56 MAXIMUM
Reference Document: JEDEC Publication 95, MS-018
853111AV-01
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REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
Marking Package 28 Lead PLCC 28 Lead PLCC 28 Lead "Lead-Free" PLCC 28 Lead "Lead-Free" PLCC Shipping Packaging Tube 500 Tape & Reel Tube 500 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS853111AV-01 ICS853111AV-01T ICS853111AV-01LF ICS853111AV-01LFT ICS853111AV-01 ICS853111AV-01 TBD TBD
NOTE: Par ts that are ordered with an "LF" suffix to the pat number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark. HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853111AV-01
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REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Features Section - added Lead-Free bullet. Added Additive Phase jitter section. Date 4/25/05
Rev
Table
Page 1 5
853111AV-01
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REV. A APRIL 25, 2005

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